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? semiconductor components industries, llc, 2011 april, 2011 ? rev. 1 1 publication order number: CAV24C02/d CAV24C02, cav24c04, cav24c08, cav24c16 2-kb, 4-kb, 8-kb and 16-kb i 2 c cmos serial eeprom description the CAV24C02/04/08/16 are 2 ? kb, 4 ? kb, 8 ? kb and 16 ? kb respectively cmos serial eeprom devices organized internally as 8/16/32/64 and 128 pages respectively of 16 bytes each. all devices support both the standard (100 khz) as well as fast (400 khz) i 2 c protocol. data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a page write buffer, and then writing all data to non ? volatile memory in one internal write cycle. data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. external address pins make it possible to address up to eight CAV24C02, four cav24c04, two cav24c08 and one cav24c16 device on the same bus. features ? automotive temperature grade 1 ( ? 40 c to +125 c) ? supports standard and fast i 2 c protocol ? 2.5 v to 5.5 v supply voltage range ? 16 ? byte page write buffer ? hardware write protection for entire memory ? cav prefix for automotive and other applications requiring site and change control ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? these devices are pb ? free, halogen free/bfr free and are rohs compliant scl wp cav24cxx figure 1. functional symbol v ss sda v cc a 2 , a 1 , a 0 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information soic ? 8 w suffix case 751bd tssop ? 8 y suffix case 948al pin configurations (top view) sda scl wp v cc v ss 1 2 3 4 8 7 6 5 soic (w), tssop (y) pin function pin name a0, a1, a2 function device address input sda serial data input/output scl serial clock input wp write protect input v cc power supply v ss ground nc no connect cav24c__ 16 / 08 / 04 / 02 nc /// nc nc nc nc nc a 0 a 1 a 1 a 2 a 2 a 2 /// /// free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 2 table 1. absolute maximum ratings parameters ratings units storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. during input transitions, voltage undershoot on any pin should not exceed ? 1 v for more than 20 ns. voltage overshoot on pins a 0 , a 1 , a 2 and wp should not exceed v cc + 1 v for more than 20 ns, while voltage on the i 2 c bus pins, scl and sda, should not exceed the absolute maximum ratings, irrespective of v cc . table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program / erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c. table 3. d.c. operating characteristics (v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz 1 ma i ccw write current write, f scl = 400 khz 2 ma i sb standby current all i/o pins at gnd or v cc t a = ? 40 c to +125 c 5 a i l i/o pin leakage pin at gnd or v cc 2 a v il input low voltage ? 0.5 0.3 x v cc v v ih input high voltage a 0 , a 1 , a 2 and wp 0.7 x v cc v cc + 0.5 v scl and sda 0.7 x v cc 5.5 v v ol output low voltage v cc > 2.5 v, i ol = 3 ma 0.4 v table 4. pin impedance characteristics (v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter conditions max units c in (note 4) sda pin capacitance v in = 0 v, f = 1.0 mhz, v cc = 5.0 v 8 pf other pins 6 pf i wp (note 5) wp input current v in < v ih , v cc = 5.5 v 130 a v in < v ih , v cc = 3.6 v 120 v in < v ih , v cc = 2.5 v 80 v in > v ih 2 i a (note 5) address input current (a0, a1, a2) product rev h v in < v ih , v cc = 5.5 v 50 a v in < v ih , v cc = 3.6 v 35 v in < v ih , v cc = 2.5 v 25 v in > v ih 2 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 5. when not driven, the wp, a0, a1 and a2 pins are pulled down to gnd internally. for improved noise immunity, the internal pull ? down is relatively strong; therefore the external driver must be able to supply the pull ? down current when attempting to driv e the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull ? down reverts to a weak current source. free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 3 table 5. a.c. characteristics (note 6) (v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (note 6) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to data out valid 3.5 0.9 s t dh data out hold time 100 100 ns t i (note 6) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (notes 7, 8) power ? up to ready mode 1 1 ms 6. test conditions according to ?ac test conditions? table. 7. tested initially and after a design or process change that affects this parameter. 8. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input drive levels 0.2 x v cc to 0.8 x v cc input rise and fall time 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference level 0.5 x v cc output test load current source i ol = 3 ma; c l = 100 pf free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 4 power ? on reset (por) each cav24cxx* incorporates power ? on reset (por) circuitry which protects the internal logic against powering up in the wrong state. a cav24cxx device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por feature protects the device against ?brown ? out? failure following a temporary loss of power. *for common features, the CAV24C02/04/08/16 will be referred to as cav24cxx. pin description scl : the serial clock input pin accepts the serial clock generated by the master. sda : the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a0, a1 and a2 : the address inputs set the device address when cascading multiple devices. when not driven, these pins are pulled low internally. wp : the write protect input pin inhibits all write operations, when pulled high. when not driven, this pin is pulled low internally. functional description the cav24cxx supports the inter ? integrated circuit (i 2 c) bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cav24cxx acts as a slave device. master and slave alternate as either transmitter or receiver. i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull ? up resistors. master and slave devices connect to the 2 ? wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see ac characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 2). the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake ? up? call to all receivers. absent a start, a slave will not respond to commands. the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8 ? bit serial slave address. for normal read/wri te operations, the first 4 bits of the slave address are fixed at 1010 (ah). the next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. the last bit of the slave address, r/w, specifies whether a read (1) or write (0) operation is to be performed. the 3 address space extension bits are assigned as illustrated in figure 3. a 2 , a 1 and a 0 must match the state of the external address pins, and a 10 , a 9 and a 8 are internal address bits. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9th clock cycle (figure 4). the slave will also acknowledge the address byte and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. as long as the master acknowledges the data, the slave will continue transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by issuing a stop condition. bus timing is illustrated in figure 5. free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 5 start condition stop condition sda scl figure 2. start/stop timing 1010 a 10 a 9 a 8 r/w cav24c16 1010 a 2 a 9 a 8 r/w cav24c08 1010 a 2 a 1 a 8 r/w cav24c04 1010 a 2 a 1 a 0 r/w CAV24C02 figure 3. slave address bits 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) figure 4. acknowledge timing scl sda in sda out t buf figure 5. bus timing t su:sto t su:dat t dh t r t low t aa t hd:dat t high t low t hd:sda t f t su:sta free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 6 write operations byte write in byte write mode, the master sends the start condition and the slave address with the r/w bit set to zero to the slave. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the cav24cxx. after receiving another acknowledge from the slave, the master transmits the data byte to be written into the addressed memory location. the cav24cxx device will acknowledge the data byte and the master generates the stop condition, at which time the device begins its internal write cycle to nonvolatile memory (figure 6). while this internal cycle is in progress (t wr ), the sda output will be tri ? stated and the cav24cxx will not respond to any request from the master device (figure 7). page write the cav24cxx writes up to 16 bytes of data in a single write cycle, using the page write operation (figure 8). the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the data byte is transmitted, the master is allowed to send up to fifteen additional bytes. after each byte has been transmitted the cav24cxx will respond with an acknowledge and internally increments the four low order address bits. the high order bits that define the page address remain unchanged. if the master transmits more than sixteen bytes prior to sending the stop condition, the address counter ?wraps around? to the beginning of page and previously transmitted data will be overwritten. once all sixteen bytes are received and the stop condition has been sent by the master, the internal write cycle begins. at this point all received data is written to the ca v24cxx in a single write cycle. acknowledge polling the acknowledge (ack) polling routine can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write operation, the cav24cxx initiates the internal write cycle. the ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cav24cxx is still busy with the write operation, noack will be returned. if the cav24cxx has completed the internal write operation, an ack will be returned and the host can then proceed with the next read or write operation. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no impact on the operation of the cav24cxx. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the first data byte (figure 9). if the wp pin is high during the strobe interval, the cav24cxx will not acknowledge the data byte and the write request will be rejected. delivery state the cav24cxx is shipped erased, i.e., all bytes are ffh. address byte data byte slave address s a c k a c k a c k s t o p p s t a r t bus activity: master slave a 7 ? a 0 d 7 ? d 0 figure 6. byte write sequence free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 7 t wr stop condition start condition address ack 8 th bit byte n scl sda figure 7. write cycle timing a c k a c k a c k s t o p s a c k a c k s t a r t p slave address n = 1 p 15 address byte n n+1 n+p bus activity: master slave data byte data byte data byte figure 8. page write sequence 1891 8 a 7 a 0 d 7 d 0 t su:wp t hd:wp address byte data byte scl sda wp figure 9. wp timing free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 8 read operations immediate read upon receiving a slave address with the r/w bit set to ?1?, the cav24cxx will interpret this as a request for data residing at the current byte address in memory. the cav24cxx will acknowledge the slave address, will immediately shift out the data residing at the current address, and will then wait for the master to respond. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 10), the cav24cxx returns to standby mode. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a ?dummy? write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the cav24cxx acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/w bit set to one. the cav24cxx then responds with its acknowledge and sends the requested data byte. the master device does not acknowledge the data (noack) but will generate a stop condition (figure 11). sequential read if during a read session, the master acknowledges the 1 st data byte, then the cav24cxx will continue transmitting data residing at subsequent locations until the master responds with a noack, followed by a stop (figure 12). in contrast to page write, during sequential read the address count will automatically increment to and then wrap ? around at end of memory (rather than end of page). scl sda 8 th bit stop no ack data out 89 slave address s a c k d ata byte n o a c k s t o p p s t a r t bus activity: master slave figure 10. immediate read sequence and timing slave s a c k n o a c k s t o p p s t a r t s a c k slave address a c k s t a r t d ata byte address byte address bus activity: master slave figure 11. selective read sequence s t o p p slave address a c k a c k a c k n o a c k a c k d ata byte n d ata byte n+1 d ata byte n+2 d ata byte n+x bus activity: master slave figure 12. sequential read sequence free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 9 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35 free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 10 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40 free datasheet http:///
CAV24C02, cav24c04, cav24c08, cav24c16 http://onsemi.com 11 example of ordering information CAV24C02/04/08/16 (note 11) prefix device # suffix company id cav 24c16 w product number e ? g package e = automotive ( ? 40 c to +125 c) temperature range w: soic, jedec y: tssop lead finish g: nipdau t: tape & reel 3: 3000 units / reel 24c02 24c04 24c08 24c16 tape & reel (note 13) t3 9. all packages are rohs ? compliant (lead ? free, halogen ? free). 10. the standard lead finish is nipdau. 11. the device used in the above example is a cav24c16we ? gt3 (soic, automotive temperature, nipdau, tape & reel, 3,000/reel). 12. for availability of other package options, please contact your nearest on semiconductor sales office. 13. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 CAV24C02/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative free datasheet http:///

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